It is often necessary to distribute high-speed differential signals on integrated circuits. In a typical arrangement, the communications paths that are used in handing these signals take the form of a parallel set of conductors formed in one or more layers of the dielectric stack of the integrated circuit. A path of this type may sometimes be referred to as a differential transmission line pair.
During semiconductor manufacturing operations, the layers of a dielectric stack may be subject to chemical-mechanical polishing (CMP) operations. During CMP operations, the thickness of conductive lines may be affected by the presence or absence of nearby structures. Metals such as copper, from which interconnect structures are commonly formed, tend to be softer and more susceptible to thinning during polishing than surrounding silicon dioxide in the dielectric stack. A conductive line that is adjacent to a relatively small number of interconnect structures may therefore be somewhat protected during polishing by the correspondingly large amount of silicon dioxide near the conductive line. As a result, the conductive line may be thicker than expected and may have a relatively low resistance. If, however, a conductive line is adjacent to a relatively large number of interconnect structures and relatively small amount of silicon dioxide, the CMP polishing operation may be more effective than intended and the conductive line may be thinner and may have a higher resistance than expected.
When proximity-based polishing effects such as these affect the conductivity of the parallel lines in a differential transmission line pair, undesired impedance variations may be produced. These impedance variations may adversely affect performance. Communications paths based on parallel conductors may also be susceptible to cross-talk due to electromagnetic coupling with nearby communications paths.